1. Field of the Invention
The invention relates to an option fuse circuit, and more particularly, to an option fuse circuit manufactured with a single-poly CMOS manufacturing process.
2. Description of the Prior Art
Within a variety of electronic products, memories (for example, ROM, DRAM, and SRAM, etc) have always been one of the most important components, as they perform a function of storing volatile and non-volatile data. A memory comprises a plurality of memory cells, each of which is used for storing one bit of digital data. The plurality of memory cells are usually lined up in an array, and manufactured in a form of an integrated circuit using semi-conductor manufacturing processes.
During ordinary semi-conductor manufacturing processes, because it is not possible for a yield of production of integrated circuits to reach 100%, a certain percentage of defective products is expected. Therefore, during the flow from manufacturing to shipping of ICs, a product-testing step is critical and not ignorable. Only through the process of product testing can malfunctioning or unusable products due to the yield issue in a semi-conductor manufacturing process be filtered out and eliminated, guaranteeing that customers are shipped well-functioning products. Through the above description one can see that product testing is extremely important in the semi-conductor manufacturing process.
Since there are a huge number of memory cells in a memory (usually from tens to hundreds of megabytes, for example, 64 Mb or 128 Mb, etc), the probability of a malfunction happening in at least one among these many memory cells is quite high. If there is one malfunctioning memory cell in a memory, the memory will be treated as a defected product and become unusable. This causes trouble for memory manufacturers. Therefore, in general, when designing a memory, beside a main memory cell array an additional set of redundant memory cells is appended, and dedicated circuitry is used for controlling and selecting connections between the set of redundant memory cells and the memory cell array. By utilizing this technique, when some memory cells at certain addresses of the memory cell array are found to malfunction during the product-testing step, the dedicated circuitry can be used for controlling the set of redundant memory cells to replace the function of those malfunctioning memory cells. As a result, it is not necessary to eliminate the memory just because of a small fraction of malfunctioning memory cells, and costs are reduced. The above-mentioned dedicated circuitry is usually called an option fuse circuit.
Please refer to FIG. 1, which is a schematic diagram of an embodiment of an option fuse circuit 10 according to the prior art. The option fuse circuit 10 comprises a PMOS transistor P1, a PMOS transistor P2, an NMOS transistor N1, and an option fuse 12. The transistors P2, N1 are electrically connected to each other to form an inverter 14, wherein two gates are connected to each other to form an input node of the inverter 14, and two drains are connected to each other to form an output node of the inverter 14. A drain of the transistor P1 and one end of the option fuse 12 are electrically connected to the input node of the inverter 14, a gate of the transistor P1 is electrically connected to the output node of the inverter 14, and the output node of the inverter 14 is pulled out as an output node Vout of the option fuse circuit 10. Finally, sources of the transistors P1, P2 are electrically connected to a system voltage Vdd, and a source of the transistor N1 and the other end of the option fuse 12 are electrically connected to ground Vss.
Please refer to FIG. 1, FIG. 2, and FIG. 3. FIG. 2 shows a layout diagram of the option fuse 12 shown in FIG. 1, and FIG. 3 is a schematic diagram showing that the option fuse 12 shown in FIG. 2 has been cut by a laser. The option fuse 12 is usually laid out using a metal line segment or a poly line segment, and as shown in FIG. 3, during the product-testing process, the option fuse 12 can be cut by the laser according to testing results. Since the output node Vout of the option fuse circuit 10 shows different output signal values between situations of the option fuse 12 being cut and not being cut (Take the option fuse circuit 10 in FIG. 1 for example, when the option fuse 12 is not cut, Vout shows a logical “1”, i.e. a high voltage. When the option fuse 12 is cut, Vout shows a logical “0”, i.e. a low voltage), values of Vout of a plurality of the option fuse circuits 10 in the memory can be used to encode a combination of the redundant memory cells for replacing the malfunctioned memory cells in the memory array.
Please refer to FIG. 4, which is a schematic diagram of another embodiment of an option fuse circuit 20 according to the prior art. The option fuse circuit 20 comprises a PMOS transistor P3, an NMOS transistor N2, an NMOS transistor N3, and an option fuse 22. The transistors P3, N3 are electrically connected to each other to form an inverter 24. A source of the transistor P3 and one end of the option fuse 22 are electrically connected to a system voltage Vdd, and the transistors N2, N3 are electrically connected to ground Vss. When the option fuse 22 is not cut, Vout shows a logical “0”, i.e. a low voltage. When the option fuse 22 is cut, Vout shows a logical “1”, i.e. a high voltage. As the above-mentioned embodiment, values of Vout of a plurality of the option fuse circuits 20 in the memory can be used to encode a combination of the redundant memory cells for replacing the malfunctioned memory cells in the memory array.
However, in order to prevent the destruction of surrounding devices due to the laser cutting, it is usually necessary to preserve a sufficient space around the layout of the option fuse 12(22) (as shown in FIG. 2 and FIG. 3, an area of 5 μm×5 μm), and in order to proceed the laser cutting, an oxide layer on top of the option fuse 18 needs to be excavated to make an opening. However, the opening gives an entrance for contaminants, such as water vapor, to destroy surrounding devices, and this, as a result, lowers the reliability of these surrounding devices. This phenomenon is most significant when a number of the option fuse circuits 10(20) in the memory dramatically increases following an increasing memory storage space, because more option fuse circuits 10(20) brings a larger number of openings, and hence greater opportunity of contamination of devices in the memory. On the other hand, laser cutting is relatively a much more time-consuming procedure since a large number of option fuses 12(22) are required to be cut one after another during the product-testing process. The above-mentioned effect also causes a significantly long testing time.
As we know, the CMOS manufacturing process is the most popular technique to manufacture semiconductor-related products. Particularly, a single-poly CMOS manufacturing process has the advantages of low cost and easy process. Therefore, the best solution is to apply the single-poly CMOS manufacturing process to achieve a novel design to avoid the above-mentioned problems caused by using laser-cutting technology in an option fuse circuit. In addition, certain technologies according to the prior art adopt flash memories in conjunction with proper circuit designs to realize the option fuse circuit. However, the manufacturing method of flash memories is not compatible with a standard CMOS manufacturing process, and has to include an additional poly-silicon layer to increase the manufacturing costs.